1. Field of the Invention
This invention relates to semiconductor devices and more particularly to an improved conductor structure.
2. Description of Related Art
A buried bit line ROM cell is by far the most competitive ROM structure of high density ROM memories because it is contactless and hence the cell size is smaller. The dimension of a cell is determined mainly by the pitches of the word line polysilicon structures employed to connect to the cells and the buried N+ bit lines. When the cell dimension shrinks, the buried bit line N+ doping needs to be reduced to avoid the problem of short channel punch through.
A device made with the low N+ concentration produced by the reduced level of doping is sensitive to the counter doping from P- type (boron) doping for programming in the channel region.
The boron implantation with a dose &gt;1.times.10.sup.14 /cm.sup.2 in the channel area for programming also goes into the source/drain buried N+ area with an As+ implantation dose of about 1.times.10.sup.15 /cm.sup.2, which increases source/drain capacitance. Low buried bit line resistance is important because every cell will have a different bit line resistance to metal pick up contact (low resistance metallic line in contact with the contact opening.) For example, there will be one contact for every 32 cells.
FIG. 1 shows a plan view of a semiconductor device and FIG. 2 shows a sectional view of that device taken along line 2--2 in FIG. 1. For a certain design rule, the minimal opening for ROM code implantation is the same as channel area 10 in a semiconductor substrate 9 shown in FIGS. 1 and 2 where 10 is the channel area and the word line 11 is formed of polysilicon or polycide, in accordance with the state of the art and buried bitlines 14 and 14' are at right angles to word line 11.
The cross section along the direction of word line 11 taken along line 2--2 in FIG. 1 is shown in FIG. 2. The word line 11 crosses over the SDOX (Source/Drain Oxide) layer 12. The SDOX layer 12 is grown over an N+ implant area during gate oxide oxidation. SDOX layer 12 is thicker (between about 600 .ANG. about 1500 .ANG.) than the gate oxide (about 200 .ANG.) and the channel area 10 composed of a gate oxide over P- well (P- sub) area. The bit lines 14, 14' (source/drain) doped with N+ ions lie beneath the SDOX layer 12. The source and the drain regions can be interchangeable. The source and the drain are bit lines also.
Photoresist layer 15 has been added to the structure and patterned in the usual photolithographic fashion. The openings 16 are above the channel areas 10 and the boron B+ ions are implanted in subchannel area 18 beneath the channel area 10.
The implanted boron plus lateral diffusion from both the N+ area and the channel boron area results in lower N+ concentration near the source/drain edge 99 as shown in FIG. 2, which in turn, results in higher N+ resistance. Also, the formation of N+/P+ junctions (P+ represents boron doping in channel area) results in high source/drain junction capacitance (C.sub.j.) All the factors of high sheet resistance (high Rs of N+) and high junction capacitance,( high C.sub.j of N+/P+) are the challenges for high speed design of buried bit line ROM products. Note that R.sub.s (sheet resistance) as employed herein refers the value of diffused resistance per unit square of a buried bit line. The unit of R.sub.s is ohms per square. As employed herein, junction capacitance (C.sub.j) refers to source/drain to substrate junction capacitance.)
FIG. 3 is a plan view showing a region of the P+ layer 30 within a ROM opening 31 framed by the bitlines 14 and 14' and within the upper word line 11.
FIG. 4 shows a section taken along line 4--4 in FIG. 3 with the P+ layer illustrated beneath the channel area 13.
An object of this invention is to make the ROM code implantation (boron for this case) into the center part of the channel area, which can achieve the goals of enhancing programming (turning the transistor off) and preventing the P+ layer from encroaching upon or contacting with the N+ source/drain junction.